This section contains some annotated photos for some of the more interesting or challenging projects I have worked on. My first foray into hardware design centered around the design of a new high speed bus used for data acquisition in high energy physics experiments (at SLAC) and in industry. That shaped my approach to neural network system design where I was focused on the communications problem and how to move spikes around in a multiplexed fashion without losing critical timing in the signal arrival times – how to emulate a ‘connectome.’ I designed my own version of a spike event code for neural networks called STA (space-time-attribute code), and proposed it to DARPA for some funding. Afterward, I met some folks from Caltech working on what they called AER (address event representation). There was much in common, so we teamed up for a while to create the Silicon Cortex or SCX board system. I drew the first AER timing diagram and that became a working spec for neuromorphic engineering for a while.
To summarize I have designed one or more boards or worked on a bus standard for each of Fastbus, Multibus, VME bus (including VSB), SBus, PC/AT aka ISA bus, PCI bus, PICMIG, I2C, STA, AER, hierarchical AER, and custom. I also worked on telecom projects from RS232 and 423 to OC48 speeds. If you have not heard of some of those you can follow the links or read the comments for the projects that follow. I was on the Fastbus, VME bus, and Scalable Coherent Interface (SCI) standards teams. I organized a team in industry and academia to study the neural communications infrastructure problem in the early 90’s. We produced a report giving suggestions to the IEEE Microprocessor Standards Committee that were addressed in the SCI standard soon after thanks to David James at Apple and David Gustavson at SLAC. I was once USA User Committee Chair for the VME International Trade Association (VITA) for a year, and later Chair of the IEEE Computational Intelligence Society (CIS) ANN Interface Standards group for a year. I never had sufficient travel funds to accomplish much for either.
For the detail oriented, my first board level design was drawn by a draftsman using lead on an E size sheet of paper and layout done by a PCB designer digitizing lines drawn on large mylar sheets. My first design proto was all wire-wrap over a ground plane for high speed ECL. Then I moved on to using PC-based tools: PADs, Orcad, Altium, Mentor and Eagle. For programmable logic design I have used Signetix FPGA tools, MMI PALASM tools, and then manufacturer independent ABEL, CUPL, and VHDL in different varieties with a little Modelsim for MMI, TI, Cypress, Xilinx, Altera and Lattice devices. Most of my experience is in digital logic and interfacing, but with some modest analog. I have not designed any custom VLSI.