2008: UCSD ISNL Tester

Remember my description of the TI PAC20 board for the IC tester.  Gert wanted to have a tester for his hybrid neuromorphic ICs.  Any pin could be anything: analog, digital, power, ground, or no connect.  How do you design a generic tester that could accommodate any 48 pin DIP chip prototype.  Aha!  Tester per pin architecture like the T.I. Impact 1.  We had Xilinx development boards with a big FPGA and embedded CPU, and cross development tools.  So we decided to run the tester with that.  So the first picture shows the tester with an on board FPGA of its own that interfaces to the remote FPGA with CPU.  The length matched lines, especially clocks, were distributed to minimize skew to the clock pins on digital logic cards.  There were two types of digital plug in cards that were configurable many ways.  One was a D to A and the other A to D.  There had to be clock termination options as well.  There was provision for multiple power supply voltages, a reset, and status LEDs plus a small breadboard area for interfacing to the DUT if needed.Neural IC testerNeural IC tester ADC pin cardNeural IC Tester DAC pin card

Everything checked out.  We got involved in the exciting Synapse proposal effort, and the software for this went on a back burner until others picked it back up.  This was a large board, and it was only half of the system.  It required another Xilinx XUP series board comparable in size to drive it.  When all assembled it would cover the top of a small file cabinet next to my desk for debug.