1991b-3: Bell Labs ANNA

I started getting lots of contract work with Bell Labs Neural Network group.  This one was for Eduard Sackinger et al.  It was a high speed pipeline sequencer to feed their ANNA chip (Analog Neural Network ALU).  It had 4 Xilinx 4004 FPGAs.  I was not VHDL literate then.  Eddie did all that firmware, and their team all made it do useful work in high speed character recognition.  I did the schematics, etc. with PCB layout contractors routing.

Bell Labs ANNA with DSP32C on VME

The ANA boards evolved through 2 generations on 2 platforms.  See also their NIPS paper and IEEE paper 1 and IEEE paper 2.  Here is the 1st generation before the high speed version above.

NET32K chip with DSP32C and SRAM on VME bus NET32K chip with DSP32C and SRAM on AT Bus