1994: Oxford Silicon Cortex

Now things get interesting.  In 1989 while commuting 180 miles daily to my first contract job in Long Beach I developed a method for scalable neural communications called STA, or space-time-attribute code.  The code represent the time and the geometrical location in 3D space of an event with optional extra attribute about the event.  I was keeping it under wraps as a trade secret waiting for a response from DARPA on a proposal that never came.  A year or two later Misha Mahowald was invited to give a talk at UCSD about her Silicon Retina project at CalTech.  She described the Address-Event protocol, known as AER.  She later confided that she got the ideas for that from Mass Sivilotti at CIT.   I read his thesis, and it was very similar to STA though not identical.  So we had come up with very similar ideas independently.  They got the funding to pursue AER.  DARPA pretty much ignored my proposal.  I decided to team up with Misha and her P.I. neuroscientist Rodney Douglas to help them build a system for the ‘silicon cortex chip’ (SCX) they were working on.

I thought a DSP would help them with its fast multiply and accumulate.  We discussed the popular Transputer approach and others.   Misha finished her PhD and joined Rodney at Oxford.  They got advice from myself and from local folks there, including Adrian Whatley who joined their team, and they decided to use a TMS320C50.  I convinced them to use VME bus so they could ramp up to a big system.  I worked with them using email over a 1200 baud modem until we had a specification.  I helped Adrian decide what registers he needed in the VME interface.  Rodney and Misha needed a specific bussing scheme for interchip communication.  I encouraged use of FIFOs, and I found a good daughterboard connector so that they could put up to about 8 chips on a double wide board, and with VME they could put several boards in one chassis. They were just trying to get one or two chips to work while I was thinking on a much larger system integration scale.  When I asked for an AER timing diagram, no one knew exactly what I meant (a data sheet view).  Since I was implementing bus protocols in CPLDs, I needed one.  So I produced one that let timing reveal its own representation in our instantiation.

Here is the block diagram I drew to make sure we were all on the same page since we were working between San Diego and UK.

SCX Architecture Diagram

Note that I snuck in two copies of a prototype of my STA in this system on the VME auxiliary connector.  They were not at all interested in that, but they tolerated me doing it.  STA was different because rather than “Let time be its own representation” (Carver Mead’s Mantra), it used time stamps, and it had a clock to speed up the transfers tested up to 25 MHz with an event transmitted on every clock by using arbitration in parallel with transfers.  That was a trick which I think originated with Fastbus (Downing and Paffrath) and was also used in Nubus in the early MAC PCs.   So we had a system supporting 50 million AERs per second, or a lesser number of STAs with geographic domain address filters and time stamp information packets.  “Time did not allow full realization,” (pun intended).

This board was complex, and needed lots of programmable logic (13 CPLDs).  Cypress Semi was offering free VHDL tools with their CPLD family, so I went with them.  However their tools turned out to be very flakey.  The project budget did not have the time or money for anything better.  I had agreed to deliver them 4 boards for ~$28K.  They nudged that up a little more later and covered some parts costs.  I had expected to be done in a few months.  The Cypress tools caused me so much problem that I ended up putting in 80 hour weeks for a year.  Without sufficient funds for a subcontractor, I had to do the PCB layout myself with PADs.  That was another learning experience since I only had ever used PADs for placements before that letting subcontractors do the layout.  This time I did it all, double sided surface mount, mixed analog and digital, and made it fit in a single wide VME module.  Adrian Whatley did all the software except for the FORTH test loops I did to prove the VME registers worked.

There was some debug confusion for a while when things did not work until a bug was found in the SCX chips.  I worked on SCX for 2 years that were crammed into 1 year for about 1/2 years pay.  I did that wanting very much to work closely with the academics in neuroscience and neuromorphic engineering.  Delivery was late, but they were patient.  They had moved from Oxford to EPFL, and resumed debug there later.  I got invited to Telluride to present once or twice as a result.  I thought of teaming  with them again and going for bigger funding to create a neural internet using STA, but folks balked at signing an NDA.  I finally decided after a couple more years to disclose my grand plan at a neuromorphic conference in Spain, but the paper was not accepted.  That really hurt.  I stopped working on SCX thereafter.  Years later we did get a chapter in a milestone book on Pulsed Neural Networks.  But the big ideas about the neural internet had to wait for almost a decade until big system integration issues started to be taken seriously.   Now people are designing their systems to assure consistent on-time message delivery.


SCX top


SCX bottom
 really did use the bottom, and everything fit within VME single wide board specs.

Obviously, I’m no photographer.  My daughter Michelle now runs that Department.

Both sides of the Silicon Cortex enhanced VME boardSCX top side using TI TMS320C50