George Works at SAIC (Science Applications International Corp) was in a big race to beat Hecht-Nielsen Neurocomputers with the bestest, fastest, baddest neurocomputer to ever be. We patented a modified Harvard 3-way memory, multiply and accumulate architecture that was implemented with two bit-slice processor modules. It ran at 11 MHz doing 22 megaflops. It had 12 meg of DRAM on board for ‘large’ simulations. We had custom software for NN model development. My part was all the main board placement, schematic entry, manage routing, and all the PLD design. There was also no small debug and little sleep.
(5 daughter card types, 17 total)
It is always a good idea to be careful what you wish for. When done the bipolar bit-slice processors were too power hungry for the PC bus. We had to blow on it hard for cooling and stick a sizable power supply on top of the PC to run it. In the end, Work’s masterwork arguably worked; but on questioning that, I was out of work and eventually the whole NN division went entropic.