This VME board was called the PAC20. It was a Motorola 68020 with a separate FPU. It had a VSB interface, DRAM, and a place for two mezzanine boards for expansion. Today it looks rather straightforward. Back then it was state of the art because surface mount was a new IC packaging technology, and TI was a leader to promote and master its production. AFIK this was the first all surface mount VME processor board, and it was well noted by industry experts resulting in an invitation for me to be the Chair of VME International Trade Association (VITA) User Groups. This board was the product of 4 engineers and a tech. I was the lead architect. Keith Tuminello and Steve Florence got the schematics and layout entered into our early PC-based CAD tools. Ken Greely worked on software drivers. I did all the PLD and logic designs with CUPL and DATA I/O and guided the IC placements. Four of these CPUs went into a VME chassis with other support boards to create the controller for 4 TTL semiconductor test heads like the one shown below. Each head could test devices with up to 64 pins and using a tester I/O board driver per pin architecture. The head shown is partly populated. I also contributed to the radial backplane design. I forgot the IC tester system product name. It loaded, tested, and sorted the ICs into speed bins at production speeds. There were many other people from 3 groups in our Process Automation Center branches groups that designed the tester.